ICMTS

IEEE 2006

International Conference on

Microelectronic Test Structures

March 6 – 9, 2006

Hyatt Regency on Town Lake

Austin, Texas USA

Conference Headquarters

16220 South Frederick Ave., Suite 312

Gaithersburg, MD 20877

301-527-0900 x104 w Fax: 301-527-0994 wendyw@widerkehr.com

Sponsored by the IEEE Electron Devices Society

Dear Technologist,

I am happy to invite you to the 2006 International Conference on Microelectronic Test Structures (ICMTS). The 19^th annual ICMTS will be held at the Hyatt Regency Hotel in Austin, Texas, USA on March 6th – 9th, 2006. The IEEE Electron Devices Society is sponsoring the 2006 International Conference on Microelectronic Test Structures. The purpose of this conference is to bring together designers and users of test structures to discuss recent developments and future directions in the use of test structures for semiconductor process evaluation.

Test structures have played a critical role in the rapid advancement of semiconductor technology. These structures, uniquely designed to isolate and emphasize individual artifacts of the technology, have allowed technologists to characterize and control the semiconductor manufacturing process and understand the fundamental properties of the technology. The International Technology Roadmap for Semiconductors identifies many of the challenges that lie ahead as technology continues to progress and test structures will be a major factor in meeting these challenges. Moore’s Law continues due to advanced materials, designs, and methods exposed by microelectronic test structures.

ICMTS began with an inaugural event in 1984 as the IEEE VLSI Workshop on Test Structures and became an IEEE Conference in 1988. ICMTS has provided a forum for the test structure design and user community to meet and discuss these important challenges and report on the most recent developments in this field. To this end ICMTS focuses on the design, fabrication, and characterization of test structures for process and material evaluation, reliability and process failure analysis, manufacturing process control, device and circuit modeling, sensors and devices as well as associated measurement techniques and data analysis. ICMTS is one of the few international IEEE-sponsored conferences that move between Europe, Asia, and the USA in a three-year cycle. The conference maintains an informal friendliness through ample social activities. Coffee breaks, hosted lunches, and a banquet allow delegates the chance to interact frequently, meeting others in their field and sharing common experiences.

Original papers presenting new developments in silicon, III-V compounds, and nanotechnology microelectronics test structure research, implementation, and applications as well as test structures aimed at new materials and devices characterization are presented. Papers are selected based upon the merit of the work and to demonstrate the broad spectrum of test structure design and use by a worldwide community.

I am very pleased to present our invited speakers for ICMTS 2006, including a keynote address by Dr. Hans Stork, Chief Technical Officer, Texas Instruments, a lithography talk by Chris Mack, founder of FINLE Technologies, and a Design for Manufacturing Characterization lecture by Konrad Young, Director of R&D for TSMC.

On Monday, March 6, a Tutorial Session will be held. Expert speakers will lecture on these topics:

Test Structure Basics Anthony Walton, U. of Edinburgh

Sub 0.1um Reliability Vijay Reddy, Texas Instruments

Regression Statistics Will Guthrie, NIST

Pulsed I-V Technique Yuegang Zhao, Keithley Instruments

MEMS Test Structures Gary Fedder. Carnegie Mellon U.

System-in-Package Johan Klootwijk, Philips

RF Characterization Franz Sischka, Agilent

Spice Modeling Colin McAndrew Freescale

The General Sessions will start on Tuesday, March 7th, and end with a half day session on Thursday, March 9th. The general sessions are designed to be delivered as a single track to allow full participation by all delegates. The general session begins with the Keynote Address by Dr. Stork. This year’s conference consists of over 40 papers in 11 sessions. The session topics for the two and one-half days include:

Session 1: Process Characterization

Session 2: Parameter Extraction

Session 3: Memory

Session 4: RF

Session 5: Special Panel on RF Noise

Session 6: Yield

Session 7: CD Metrology

Session 8: MEMS

Session 9: Matching

Session 10: Device Characterization

Session 11: Capacitance

Session 5, the special session on RF noise measurement techniques, is new and will be introduced at ICMTS 2006. All lectures sessions are held sequentially as one track, with ample time for fruitful discussion among delegates to the conference. The Technical Program Committee will present a Best Paper award. There will be an equipment exhibition relating to test structure measurements. A Texas-styled banquet will be held on Wednesday night, and a post-conference excursion exploring Austin will be available.

Austin, known as the Silicon Hills of semiconductor technology, is a center of semiconductor activity. Companies such as SEMATECH, ATDF, Freescale, AMD, Spansion, Samsung, Silicon Labs, Cypress, Cirrus Logic and many others have facilities here. In addition, over 50,000 students at the University of Texas make U.T. one of the largest universities in the U.S., and The University includes an active semiconductor research department in Austin. But Austin is more than high-tech. Austin is a center for many types of music, holding the South by Southwest Music Conference the week after ICMTS. The Star of Texas Rodeo is also held in March. Austin is an active city, with running trails in city parks, and many lakes and rivers to enjoy. Finally, Austin is the capitol of Texas.

For those with further interest in microelectronic test structures, past ICMTS conference proceedings are available from the IEEE. In addition, more information can be found at http://www.see.ed.ac.uk/ICMTS/.

I look forward to your participation in ICMTS in Austin in 2006!

Bill Verzi

General Chairman of ICMTS 2006

Senior Member of Technical Staff

Semiconductor Process and Device Evaluation

Agilent Technologies

12401 Research Blvd.

Bldg. 1, Suite 100

Austin, Texas USA 78759

(512) 257-5833

bill_verzi@agilent.com

GENERAL INFORMATION

The 2006 IEEE ICMTS will be held at the Hyatt on Town Lake in Austin, Texas. The Conference headquarters hotel will provide guest accommodations as well as meeting facilities for all attendees. The technical program, consisting of ten sessions of contributed papers will be held March 7-9. A tutorial short course will be offered on Monday, March 6.

CONFERENCE REGISTRATION

Payment of the TECHNICAL SESSION registration fee entitles the registrant to one copy of the Technical Digest, entrance to all technical sessions and the exhibit hall, and all social events.

Payment of the SHORT COURSE registration fee entitles the registrant to one copy of the Short Course Workbook and luncheon. Short Course participants must register in advance.

For Advance Registration, complete the Registration Form and mail the form with payment to the Conference Headquarters. Advance registration forms must be received by the Conference Headquarters NO LATER THAN February 17, 2006 in order to receive the reduced registration fee. Registrations received after February 17 will be charged the late registration fee. Short Course participants should register in advance to guarantee a space at the course. On-site short course registration will only be accepted based on space availability.

If you fax your registration form, you must included credit card information and a 5% processing fees for the credit card transactions

Mail or fax your conference registration form and remittance to: 2006 ICMTS Conference

16220 South Frederick Ave., Suite 312

Gaithersburg, MD 20877

1-301-527-0900 x104 • Fax: 1-301-527-0994

Email: wendyw@widerkehr.com

CANCELLATIONS: Refund requests must be received, in writing, by February 21 in order to receive a full refund, less a $25.00 processing fee. Due to financial commitments, refund requests received after February 21 cannot be guaranteed.

IEEE Members: In order to qualify for the member fees, you must list your IEEE membership number.

	ADVANCE (by February 17)	REGULAR (after February 17 and on-site)
Technical Session
IEEE Member	$420	$480
Non-Member	$470	$530
Student	$275	$330
Short Course (ADVANCE Registration Only)
IEEE Member	$280	$300
Non-Member	$280	$300
Student	$140	$140

HOTEL RESERVATIONS

DEADLINE: FEB. 10, 2006

A block of rooms has been reserved at the Hyatt on Town lake, Austin, Texas. To make a reservation, complete the enclosed Hotel Reservation form and return it, along with one night’s lodging to:

Hyatt on Town Lake

208 Barton Springs Road

Austin, TX 78704

Reservations: 800-233-1234

Tele: 512-477-1234 Fax: 512-480-2069

Rates: $139 + tax single/double

HOTEL RESERVATIONS MUST BE RECEIVED BY FRIDAY, FEBRUARY 10 to guarantee the conference rate.

All changes and cancellations should be made directly with the hotel. It is the responsibility of each participant to make changes or cancellations no later than 48 hours prior to scheduled arrival. Room reservations will be held until 6:00 p.m. unless a later time is guaranteed by a credit card. Rooms are generally not available for check-in until 3:00 p.m. on the day of arrival.

TECHNICAL SESSION INFORMATION

The Technical Sessions will be held in the Texas Ballroom V.

EQUIPMENT EXHIBITS: ICMTS vendor exhibits will be displayed in the Texas Ballroom IV on Monday, March 6 from 6:00 p.m. and will remain on display until 12:00 noon on Thursday, March 9. A Welcoming Reception will be in the hall on Monday evening.

If you would like to exhibit at the conference, please contact Wendy Walker at the Conference Headquarters, 301-527-0900 x104; wendyw@widerkehr.com. Past exhibitors have included: HPL Technologies, Reedholm Instruments, Keithley Instruments, Silvaco, Sandia National Laboratories, TestChip Technologies, Cadence, Avanti!, Cascade Microtech, Agilent Technologies, QualiTau, Lucas/Signatone Corp. and BTA Technology.

TECHNICAL DIGEST

Extra copies of the Technical Digest can be purchased by conference through Advance Registration at a cost of $75.00. After the conference, digests will be available through the IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08855.

SOCIAL EVENTS

A Continental Breakfast (8:00 a.m. – 9:00 a.m.) will be available each day of the meeting. The conference will host luncheons on Tuesday and Wednesday.

The Conference Banquet will be held on Wednesday,

March 8 at the Salt Lick BBQ in Driftwood, Texas. Round trip bus transportation will be provided. Buses will depart from the front of the hotel starting at 5:30 p.m. One ticket is included with the registration fee, additional guest tickets may be purchased for $75.00.

An opening reception will be held on Monday evening from 6:00 p.m. – 7:30 p.m. in the Exhibit Hall.

TRANSPORTATION

By Air: The Austin Bergstrom International Airport code is AUS. ABIA is served by many airlines including American, Continental, Delta, Frontier, JetBlue, Northwest, Southwest, United and US Air/ America West. There are nearly 100 arrivals and departures daily to and from San Francisco and Los Angeles with connections to all domestic and foreign locations. The distance from the airport to the DoubleTree is approximately four miles.

By Car: Texas is a large state: The drive from either Houston or Dallas will be 3-4 hours.

Airport Transportation: Taxi service from the airport will be approximately $20.00.

Rental Cars: Several rental car agencies are located at the Austin Airport: Avis, Budget, Dollar, Hertz, National, and Thrifty.

Around town:

The Hyatt Hotel is located within 6 blocks of innumerable bars and restaurants. Free “Dillo” buses operate until 3am and have routes that stop adjacent to the Hyatt. For more information, see: www.capmetro.org/riding/downtowntrollies.asp

and take specific note of the Starlight route, and the combined map link.

MESSAGES

A message board will set up in the registration area for conference attendees. Call the hotel at 512-347-1234 and ask for the ICMTS Registration Area.

WEATHER

The weather in Austin should average 70°F high / 47°F low. Historical ranges are 55-82°F High and 34-64°F Low. The historical probability of rain for March 6-9 is 28%, but only 6% chance of rain over 0.1”. The average humidity is between 40-95%.

AUSTIN AREA ATTRACTIONS

Austin, the state capitol of Texas, is the gateway to the Texas Hill Country, surrounded by rolling hills and sparkling waterways. From the graceful State Capitol building to the historical area, Austin is filled with Texas charm. Each night from March through October, more than 1.5 million Mexican free-tailed bats fly out from beneath the Congress Avenue Bridge that spans Town Lake, next to the Hyatt Hotel. Also, within walking distance of the hotel or take a short ride on the “Dillo” bus to the Sixth Street area for Austin’s musical nightlife. Clubs featuring live bands playing Country, blues, rock and roll, Western swing, hip-hop, Tejano and Latin jazz are all around. Austin also has wonderful museums, from the Texas State History Museum, to the LBJ Presidential Library and Museum and the Austin Museum of Art and the Umlauf Sculpture Garden.

Immediately following the conference is the South by Southwest Festival (www.sxsw.com) where filmmakers, musicians and multi-media artists from around the world gather to showcase music, film and interactive multi-media. Also, the Star of Texas Fair and Rodeo takes place on March 11 - 25 (www.staroftexas.org) Austin goes cowboy as PCRA competitors hit the arena and area students exhibit prize livestock. Headline entertainment is also scheduled.

TOUR PROGRAM

Thursday, March 9

2:30 p.m. - 4:30 p.m.

$40 per person

Historic Austin Walking Tour

Austin's historic downtown lends itself to enjoying the sites best by walking. Enjoy an up-close look at Austin.

Our motor coach will pick you up at the Hyatt and take you to the Texas State Capitol, constructed of pink granite from nearby Granite Mountain in Burnet County, is situated on approximately 26 acres of land and was modeled after the Nation's Capitol in Washington, D.C. Construction began in 1882 and was completed in 1888. It was designated a National Historic Landmark in 1986.

We continue to walk past the Governor's Mansion, built in the Greek Revival style in 1856. Austin was a pioneer town of about 3,000 when the legislature authorized $17,000 to erect and furnish a residence and outbuildings for the governor. The Mansion has been the home of every Texas governor since 1856 and is the nation's fourth oldest mansion still used as a governor's residence.

We continue to the Bremond Block, a rare collection of homes in Austin's Central Business District. What has survived in the midst of downtown is a rare collection of homes - most notably an entire block of houses belonging to members of a single family.

This tour includes transportation via motorcoach from the Hyatt Town Lake to the starting point of the tour and return transportation to the Hotel at the conclusion of the tour. Two tour guides will be present to conduct the tour.

TUTORIAL SHORT COURSE:

Monday, March 6, 2006

8:30 Registration

Introduction - Richard A. Allen, NIST

1.     Test Structure Fundamentals, Anthony J. Walton, The University of Edinburgh

This presentation will begin with a review of test chips briefly detailing their history and their application. The presentation will include a brief review of test structures for measuring sheet resistance, line width and contact resistance. Measurement and equipment issues will be addressed focusing on procedures for obtaining accurate and repeatable measurements.

Anthony J. Walton is professor of Microelectronic Manufacturing in the School of Engineering and Electronics at the University of Edinburgh. He has been actively involved with the semiconductor industry in a number of areas associated with silicon processing which includes both IC technology and micro-systems. For the 20 years he has had a direct interest in the design, fabrication and measurement of microelectronic test structures and has taken an active role in the organisation of ICMTS. He played a key role in setting up the Scottish Microelectronics Centre (SMC) which is a purpose built facility for R&D and company incubation consisting of approximately 300 m² of class 10 clean rooms. He has published widely on test structures and is an associate editor of the IEEE Transactions on Semiconductor Manufacturing.

2. An Introduction to Sub 0.1um CMOS Reliability, Vijay Reddy, Texas Instruments

A combination of new materials and reduced feature sizes has brought a number of reliability challenges to the semiconductor industry. In this tutorial, front-end reliability issues to be described include:

• Gate Oxide

• Hot Carrier

• NBTI

At the back-end (interconnect), the switch to copper metallization and low-k dielectric leads to emphasis on:

• Electromigration

• Stress-Induced Voiding

• Inter/Intra-level Dielectric

• Plasma charging

Measurement techniques to characterize these effects will be described in this tutorial session.

Vijay Reddy is a member of the Technical Staff at Texas Instruments, Dallas, TX. After receiving the Ph.D. in Electrical Engineering from The University Of Texas At Austin, he joined TI and has worked on several reliability topics concerning transistor/circuit/product reliability and qualification methodologies in DRAM, embedded flash, and logic technologies. He has published more than 20 papers and has several patents issued and pending. He has served on the technical program committee of the International Reliability Physics Symposium (IRPS) for several years and has presented tutorials on CMOS Reliability at IRPS (2002-2004). He is the recipient of the 2002 and 2004 IRPS Outstanding Paper Awards for work on NBTI and the 2003 ESD Symposium Best Paper and Best Presentation Awards.

3. Nonparametric Regression Methods for Modeling Physical Science and Engineering Data, Will Guthrie, NIST Statistical Engineering Division

Non-parametric regression is a type of regression analysis in which the functional form of the relationship between the response variable and the associated predictor variables does not need to be specified in order to fit a model to a set of data. There are many different methods for non-parametric regression, which often use different types of simple, local models in different sections of the data to build up an overall model of the data. This makes non-parametric regression a good competitor to non-linear regression for modeling situations in which a theoretical model is not known, or is difficult to fit. Non-parametric regression models can generally be used for the same types of applications, estimation, prediction, calibration, and optimization, that traditional regression models are used for. This tutorial will introduce some popular non-parametric regression methods and compare and contrast how they work. Concepts will be illustrated with microelectronic test structure data and other examples from NIST work.

Will Guthrie received a B.A. degree in mathematics from Case Western Reserve University in Cleveland, Ohio in 1987 and a M.S. degree in statistics from The Ohio State University in Columbus, Ohio in 1990. He is a currently a mathematical statistician in the Statistical Engineering Division at the National Institute of Standards and Technology in Gaithersburg, MD. For the last sixteen years he has collaborated with NIST scientists and engineers on applied research in a wide range of areas including semiconductor and microelectronics applications, building materials and fire science applications, and chemical science applications. His statistical interests include experiment design, uncertainty assessment, Bayesian statistics, calibration, modern regression methods, and statistical computation.

4. Characterizing Transient Device Behavior using Pulse I-V Technique, Yuegang Zhao, Keithley Instruments

This tutorial describes common practices to use pulse I-V technique to characterize transient device behavior due to self heating or charge trapping. Main topics covered include:

· The needs for pulse I-V measurement, especially ultra-short pulse I-V measurement

· Different versions of test setups for ultra-short Pulse I-V measurement, advantage/disadvantage of each setup, and potential cause of noise and errors due to setup

· Error analysis of pulse I-V measurement on transistors

· Test structure design recommendations

Yuegang Zhao received his MBA from Case Western Reserve University (2005), M.S. in Semiconductor Physics from the University of Wisconsin, Madison (2000), and his B.S. in Physics from Peking University, Beijing, China (1997). He joined the Semiconductor Business Group of Keithley Instruments Inc. in 2001 and is a lead applications engineer. He has worked on various device characterization and reliability test techniques including RF CV measurement on ultra-thin gate oxide, multi-site parallel NBTI testing with minimized relaxation, and pulse I-V characterization of FETs with high K gate and SOI devices. He has authored and co-authored more than 15 publications in the last two years in technical journals, magazines and conferences. He has 2 patents pending on pulse I-V test techniques.

5. Microelectromechanical Characterization Test Structures, Gary K. Fedder, Carnegie Mellon University

Proper MEMS design requires one to know values for process design rules and non-electronic material properties. Much research has been accomplished toward extraction of these values; however, few universally accepted methodologies exist for MEMS, in stark contrast to IC device and process extraction. Design rules unique to MEMS primarily are associated with microstructural release from the substrate, that is, allowable widths of structures and air gaps nearby. The precise width and height of devices after release is very important to measure, as the mechanical models depend directly on these values. The most important material properties for almost all MEMS include Young’s modulus, residual stress and residual stress gradients. The tutorial focuses on methods and associated test structures to extract these design rules and properties with implementation in post-CMOS micromachined technologies. Practical challenges to automated extraction and design issues specific to CMOS-based MEMS are discussed.

Gary K. Fedder is a Professor at Carnegie Mellon University holding a joint appointment with the Department of Electrical and Computer Engineering and The Robotics Institute. He received the B.S. and M.S. degrees in electrical engineering from MIT in 1982 and 1984, respectively, and the Ph.D. degree from U. C. Berkeley in 1994. From 1984 to 1989, he worked at the Hewlett-Packard Company on circuit design and printed-circuit modeling. He received the 1993 AIME Electronic Materials Society Ross Tucker Award, the 1996 Carnegie Institute of Technology G.T. Ladd Award, and the 1996 NSF CAREER Award. Currently, he serves as a subject editor for the IEEE/ASME Journal of Microelectromechanical Systems, on the editorial board of the IoP Journal of Micromechanics and Microengineering and as co-editor of the Wiley-VCH Sensors Update and Advanced Micro- and Nanosystems book series. He served as general co-chair of the 2005 IEEE MEMS Conference. He has contributed to over 100 research publications and several patents in the MEMS area. His research interests include microsensor and microactuator design and modeling, integrated MEMS manufactured in CMOS processes and structured design methodologies for MEMS.

6. System-in-Package: Combining passives and active devices heterogeneously, Johan Klootwijk, Philips Research

Reducing the passive components count and higher miniaturization levels are a major challenge in the wireless communication industry. With increasing multiple modes and frequency bands, decreasing phone form factors and integration of 3G, Bluetooth, FM radios, RF transceivers for instance require a more accurate performance of the passive components. Here, System-in-Package (SiP) technology is one of the fastest growing technologies offering highly flexible and low-cost integration and packaging solutions. The flexibility, time-to-market and cost savings are by far the driving forces favoring SiP technology over System-on-Chip solutions.

Characterization and control of SiP-technologies require common test structures as well as some more dedicated test structure solutions (e.g. wafer level testing, lifetime testing, high frequency behavior) This tutorial presents an overview of SiP concepts with their underlying technologies, test structures and test issues towards high performance RF system-in-package solutions.

Johan H. Klootwijk was born in Hengelo, The Netherlands, on June 2, 1969. He received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Twente, Enschede, The Netherlands, in 1993 and 1997, respectively. His Ph.D. dissertation dealt with the development, characterization and application of deposited interpoly dielectrics for non-volatile memories. In October 1997, he joined the Philips Research Laboratories, Eindhoven, where he was involved in the development and characterization of Si and SiGe bipolar transistors, SOI/SOA technologies and reliability of thin dielectrics. He received the best paper award for his contribution on the ESSDERC conference in 2001. After that he worked on the development of InP based HBTs and InP systems for wideband RF applications. His current research activities are in the field of passive integration, high density capacitors and System-in-Package solutions. Dr. Klootwijk was the tutorial chairman of the ICMTS 2002 in Cork, Ireland, 2002.

7. HF Characterization of Silicon Devices, with Special Emphasis on Calibration and De-Embedding Verification, Franz Sischka, Agilent EEsof-EDA

Characterizing silicon devices has become more challenging due to the improved speed performance of modern technologies. This implies the need to pay more attention to accurate HF characterization measurements and especially to reliable verification procedures. This includes verifying the network analyzer calibration quality and ensuring that the correct HF signal level is applied to the components, in order to avoid unrealistic S-parameter measurements. Another important topic is an accurate de-embedding. For on-wafer measurements, the measurement results of the de-embedding dummy structures should be verified first, before the diodes or the transistors can be de-embedded from these parasitics. The final challenge for nonlinear devices is to combine the HF measurements with consistent DC measurements, considering for example different self-heating effects during DC and S-parameter measurements. The tutorial will give an overview about practical methods to obtain reliable and accurate HF measurement results, how to interpret S-parameter curves, and how to inspect the S-parameter data with underlying standard circuit schematics.

Franz Sischka studied Electronic Communication Engineering at the University of Stuttgart, Germany, where he received his Diplom-Ingenieur and Ph.D. degrees in 1979 and 1984. After joining Hewlett-Packard in Germany, he worked in the R&D in the fiber optics group at HP Boeblingen. Since 1989, he is consultant for Agilent-EEsof's simulation and modeling software tools.

He has given invited device modeling tutorials at the VLSI 1999 (Lisbon) and also at the ICMTS (1999 Gothenburg, 2000 Monterey and 2005 Leuven) as well as at the MIXDES 2001 (Zakopane) and at the Wireless Design Conference 2002 (London) conference. Also, he is the author of Agilent's IC-CAP Modeling Reference book.

http://eesof.tm.agilent.com/docs/iccap2002/iccap_mdl_handbook.html

8. SPICE Modeling: Recent Developments and Challenges, Colin McAndrew, Freescale Semiconductor

This tutorial will review major recent developments in SPICE modeling, and highlight some areas that are becoming major challenges. With the recent Compact Model Council decision to standardize on PSP as the next generation MOSFET model, the face of MOSFET modeling is changing from threshold-voltage based to surface-potential based models. Details of the different model types will be reviewed, and the symmetric linearization method, which is at the core of PSP, will be presented. It is elegant, simple, and accurate, and is arguably the most significant advance in MOSFET modeling in the past 20 years; but it is not in text books yet and so is not widely known. Verilog-A has emerged as the language of choice for SPICE model development, and this will be reviewed. Statistical variations continue to be an active area for modeling, and changes in the nature of variations as CMOS technologies advance, and how they should be modeled, will be highlighted. Proximity effects and interconnect parasitics are attracting a lot of interest at present, and work in these areas will be reviewed.

Colin McAndrew received the Ph.D. in Systems Design Engineering from the University of Waterloo, Waterloo, Ontario, Canada. He was at AT&T Bell Laboratories for 7 years, and is at present Director, Enabling Technology, at Freescale Semiconductor, Tempe AZ. He is a Fellow of the IEEE, the Vice-Chairman of the Compact Model Council, is or has been on the technical program committees for the IEEE BCTM, ICMTS, CICC, and BMAS conferences, and is an editor of the IEEE Transactions on Electron Devices.

TUESDAY, MARCH 7

PLENARY SESSION

8:30 a.m. – 9:10a.m.

Welcome

Bill Verzi, Conference Chair

Agilent Technologies

Keynote Presentation

Electrical and Physical Characterization of 45nm CMOS Processes

Dr. Johannes M.C. (Hans) Stork, Senior Vice President and Chief Technology Officer, Texas Instruments, Inc.

Developing 45nm CMOS processes poses some new challenges to electrical characterization, from functional to parametric, and their correlation with physical features. Use of new materials and integration techniques, combinations of high performance with ultra low leakage, or analog with digital, variations across millions of components, memory stability across bias and temperature ranges, each contributes unique signatures for success or failure. Some examples will be given to illustrate how these goals might be achieved at low cost

SESSION 1: PROCESS CHARACTERIZATION

9:10 a.m. – 10:30 a.m.

Co-Chairs: Christopher Hess, PDF Solutions and Kelvin Yih-Yuh Doong, Taiwan Semiconductor Manufacturing Co.

9:10 Ring-gate MOSFET Test Structures for

1.1 Measuring Surface-Charge-Layer Sheet Resistance on High-Resistivity-Silicon Substrates, S.B. Evseev, L.K. Nanver and S. Milosavljevic, DIMES, Delft University of Technology, Delft, The Netherlands

Ring-gate MOSFET test structures have been developed with which a differential measurement technique can be used to accurately determine the surface-charge-layer sheet resistance on high-resistivity-silicon substrates. The influence of special surface passivation techniques that are designed to suppress the otherwise conductive surface channel can thus be monitored and characterized for RF transmission line applications.

9:30 −1/+0.8°C Error, Accurate Temperature Sensor

1.2 for 90nm 1V CMOS process, M. Sasaki, M. Ikeda and K. Asada, The University of Tokyo, Tokyo, Japan

This paper proposes quite accurate four-transistor temperature sensor. The sensor is featured with an extremely small area of 11.6x4.1μm² and low power consumption of about 25μW. The performance of the sensor is highly linear and the predicted temperature error is merely −1.0 ~ +0.8°C using two-point calibration within the range of 50 ~ 125°C. The sensor is implemented in ASPLA CMOS 90nm 1P6M process, operated at supply voltage of 1V, and tested successfully.

9:50 Specific Contact Resistance Measurements of

1.3 Metal-Semiconductor Junctions, N. Stavitski, M.J.H. van Dal* R.A.M. Wolters, A.Y. Kovalgin, J. Schmitz, University of Twente, Enschede, The Netherlands and * Philips Research, Leuven, Belgium

Our research comprises the manufacturing of test structures to characterize the metal-semiconductor junctions with a number of techniques and materials. An extensive subsequent physical and electrical testing of the junctions is carried out. We present our first results on specific metal-to-silicide contact resistance characterization using the Cross-Bridge Kelvin Resistor (CBKR) and Transmission Line Model (TLM), and NiSi as the silicide.

10:10 Test Structures for Study of Electron Transport

1.4 in 40 - 100-nm Nickel Silicide Features, B. Li, The University of Texas at Austin, Austin, TX

NiSi features, embedded in CD test structures, have been fabricated by annealing a nickel coating that was evaporated on narrow silicon lines with vertical and flat sidewalls and CDs between 100 nm and 200 nm. Results of E-beam direct-write lithography that is being used to fabricate NiSi test structures with sub-40nm features for the study of electron transport in large-grain structures are also shown.

10:30 BREAK

SESSION 2: PARAMETER EXTRACTION

11:00 a.m. – 12:00 p.m.

Co-Chairs: Kevin McCarthy, University College Cork and

Kjel Jeppson, Chalmers University of Technology

11:00 A New Polysilicon Resistor Model considering

2.1 Geometry Dependent Voltage Characteristics for the Deep Sub-Micron CMOS Process, S.Y. Ko*, J.S. Kim, G.H. Lim, S.K Kim, DongbuAnam Semiconductor, Gyeonggi-Do, South Korea

As minimum feature size of transistors is shrunken to nanometer scale in CMOS process, it also requires polysilicon resistor size to be applicable under micrometer range and still needs good accuracy for mixed signal or analog design. But conventional model for circuit simulation cannot describe voltage coefficient change along with different width and length resistors. In this paper, resistor geometry dependence on voltage coefficient was studied and a new model was proposed to enhance the accuracy. In addition, parameter extraction methodology for this model was introduced.

11:20 Test Structures and Measurement of Gate

2.2 Sidewall Junction Capacitance in MOSFETs

N. Hasegawa, S. Yamaura, T. Mori, and S. Yamaguchi*, Fujitsu Laboratories, Ltd., Kawasaki, Japan and *Fujitsu ltd., Tokyo, Japan

In recent deep-submicron CMOS technology, source and drain junction capacitance have come to account for a large part of short-channel MOSFET capacitance because of the decreased gate capacitance due to MOSFET scaling. As we can see from Fig. 1, MOSFET junction capacitance consists of bottom junction capacitance (c_j), isolation sidewall capacitance (c_jsw) and gate sidewall capacitance (c_jg). As c_jg occupies an especially large part of these, it is important to measure c_jg accurately. However, to our knowledge, the measurement of c_jg by itself has not been reported much, especially with short-channel transistors. In this paper we will show the test structures and a calculation method that enable c_jg extraction of short-channel transistor. We did our measurements with a 2-port network analyzer. We will also present some new results we found through measuring c_jg.

11:40 New Test Structures for Extraction of Base

2.3 Sheet Resistance in BiCMOS Technology, C. Raya, F. Pourchon, D. Celi, M. Laurens, T. Zimmer*, ST Microelectronics, Crolles, France and *Université Bordeaux, Talence, France

For process monitoring and device modeling, a new method to determine the different components of the base resistance of bipolar transistors has been developed. Dual base test structures have been improved to extract the sheet resistance value of each of these components using dc measurements. This method is applied to a state-of-art double poly ST BiCMOS technology, and results are discussed.

12:00 CONFERENCE LUNCHEON

SESSION 3: MEMORY

1:30 p.m. – 2:30 p.m.

Co-Chairs: Yoichi Tamaki, Hitachi Ltd. and

Larg Weiland, PDF Solutions, Inc.

1:30 Measurement Method for Transient

3.1 Programming Current of iTiR Phase-change Memory, K. Kurotsuchi, N. Takamura, N. Matsuzaki, Y. Matusi, O. Tonomura, Y. Fujisaki, N. Kitai*, R. Takemura, K. Osada, S. Hansawa, H. Moriyua, T. Iwaski, T. Kawahara, M. Tearo, M. Matsuoka**, and M. Moniwa**, Hitachi, Ltd., Tokyo, Japan, *Hitachi ULSI Systems, Tokyo, Japan, and ** Renesas Technology Corp., Hyogo, Japan

This paper presents a measurement method for 1 transistor – 1 resistance (1T1R), phase-change memory (PCM) devices. We fabricated a novel PCM test structure with an internal voltage measurement point, and we monitored the voltage drop between 1T and 1R. The voltage drop was accurately converted to the PCM programming current. This test structure enabled us to measure programming current of less than 100µA with the width of 100 ns. This method is essential for measuring low-power operation of PCMs and other nonvolatile memories.

1:50 Investigation of Lateral Charge Distribution of

3.2 2-bit SONOS Memory Devices Using Physically Separated Twin SONOS Structure, B.Y. Choi, C.-H. Lee*, Y.K. Lee**, H. Shin, J.D. Lee, B.-G. Park, D.-W. Kim*, S.-K. Sung*, S.-H. Lee*, B.-K. Cho*, T.-Y. Kim*, E.S. Cho*, J.J. Lee*, and D. Park*, Seoul National University, Seoul, Korea, *Samsung Electronics co., Ltd., Gyeonggi-do, Korea, and **Stanford University, Stanford, CA

The lateral charge distribution on 2-bit SONOS memory can be readily characterized using physically separated twin SONOS structure. The damascene gate and outer sidewall process successfully contribute to make the twin SONOS structure down to 80nm gate regime. Its lateral charge distribution is estimated through the SS and V_th shifts for forward and reverse reading and confirmed by the comparison with a conventional (non-separated) SONOS structure.

2:10 On the Passivation of Interface States in

3.3 SONOS Test Structures: Impact of Device Layout and Annealing Process, F. Driussi, L. Selmi, N. Akil*, M.J. Van Duuren*, and R. Van Schaijk* DIEGM, University of Udine, Udine, Italy and * Philips Research, Leuven, Belgium

This paper reports anomalous electrical characteristics of large SONOS test structures. The anomaly is attributed to the property of nitride to block the hydrogen passivation of the interface dangling bonds. Hence the passivation can occur only from the lateral sides of the device, thus implying restrictions on the dimensions and on the layout of the test structures used to study SONOS cells.

2:30 BREAK

SESSION 4– RF

2:40 p.m. – 4:00 p.m.

Co-Chairs: Franz Sischka, Agilent Home Office and

H-D. Lee, Chungnam National University

2:40 RF Measurement, Characterization, and

4.1 Verification of Cu / low-k Transmission Line Interconnects, J. Kim and D.P. Neikirk, The University of Texas at Austin, Austin, TX

In this paper we present the RF measurements for the characterization of Cu / low-k transmission line interconnects. From measured S-parameters the extracted RLCG for Cu / low-k transmission line are presented via de-embedding the pad parasitics at both ends. The relative dielectric constant and loss tangent for various dielectric materials (SiO₂, low-k2 (Novellus’ Coral low-k dielectric), and low-k1 (JSR Corp. low-k dielectric)) up to 40GHz are also extracted from the measurements. In addition this paper presents data for high frequency measurements up to 40GHz that show the precise location of microwave probes on 50micron square pads can have significant effects on the extracted per unit length RLCG parameters at frequencies above about 20GHz.

3:00 Characterisation of Advanced Multilayer De-

4.2 embedding Structures up to 50 GHz Incorporating a "Gold Standard" Reference Approach, J.A. O'Sullivan, K.G. McCarthy and P.J. Murphy, University College Cork, Cork, Ireland

Modern multi-level metallisation schemes offer the possibility of many innovative structures for frequency characterisation and de-embedding. In this paper we perform a detailed charaterisation of several such structures up to 50 GHz and show their application to measurements of a high performance HBT device. We further propose a consistency check by comparing independent DC and s-parameter measurements, to gain further confidence in the de-embedding operations.

3:20 Analysis and Modeling of Substrate Impedance

4.3 Network in RF CMOS, E. Bouhana, P. Scheer, S. Boret, D. Gloria, G. Dambrine*, M. Minondo and H. Jaouen, STMicroelectronics, Crolles, France and *IEMN, Villeneuve d'Ascq, France

This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. Using this approach on MOS transistors from 130 down to 65 nm technologies allows to point out the respective implications of the isolation layer and the surrounding well plug on high-frequency characteristics. Their impacts are studied and a new model is proposed.

3:40 Impact of Ghz Disturbances on DC Parametric

4.4 Measurements, H.P. Tuinhout and P.G.M. Baltus*, Philips Research, Eindhoven, The Netherlands and *Philips Semiconductors, Eindhoven, The Netherlands

GHz disturbance signals from mobile phones or WLAN transmitters can affect DC parametric measurements. A transistor test structure inside a wafer prober can easily turn into a GHz receiver that makes garbage of high-precision DC parametric measurements. This paper shows examples of such occurrences and presents a measurement technique for assessing the sensitivity of DC parametric measurement systems for GHz signals.

SESSION 5: RF Noise Panel

4:30 p.m. – 6:00 p.m.

Chair: Colin McAndrew, Motorola

Measurement and characterization are critical to the semiconductor industry, and the level of complexity involved increases progressively for DC I(V), low frequency AC C(V), high frequency S-parameter, low frequency noise, and high frequency noise measurement. The last has historically been a niche area important primarily for esoteric III-V devices and technologies. However, with the ineluctable advance in performance of CMOS technologies, RF-CMOS is now a commercial reality, and the need for high frequency noise characterization is becoming a mainstream activity. But it is not easy to do properly, and there is limited expertise in the industry at present. The goal of this special session on RF noise is to assemble noted experts in RF noise to pass on their knowledge, and to educate ICMTS attendees on the best practices for RF noise. Besides presentations, the session will include an open Forum time that fosters interaction between the presenters to discuss the pros and cons of various approaches, and allows the audience to participate with questions and comments.

The special session presenters are:

Dr. Dick Klaassen, Philips Research

Dr. Ali Boudiaf, Maury Microwave

Prof. Jamal Deen, McMaster University

Dr. James Randa, NIST

Dr. Ali Rezvani, RF Micro Devices

WEDNESDAY, MARCH 8

SESSION 6: Yield

8:30 a.m. – 10:10 a.m.

Co-Chairs: Ulrich Shaper, Infineon Technologies AG and Satoshi Habu, Agilent Technolgies Japan, Ltd.

8:30 Ring Oscillator Based Technique for Measuring

6.1 Variability Statistics, M. Bhushan, M.B. Ketchen, S. Polonsky and A. Gattiker, IBM Ssytems and Technology Group, Poughkeepsie, NY, *IBM T.J. Watson Research Center, Yorktown Heights, NY and **IBM Austin Research Lab., Austin, TX

Device parameter induced frequency variations in a dense array of nominally indentical ring oscillators are measured by sequentially combining the output frequencies into a single frequency modulated signal with the statistical frequency parameters read out by a standard frequency counter. The ring oscillators described are designed to capture random variations in MOSFET threshold voltages.

8:50 Methodology for Characterizing the Impact of

6.2 Circuit Layout, Technology Options, Device Engineering and Temperature on the Circuit Power-Delay Characteristics, T. Chiarella, J. Ramos, A. Nackaerts, S. Demuynck, S. Verhaegen, R. Verbeeck, M. de Potter de ten Broeck, C. Kerner, T. Hoffmann, M.Van Hove, I. Debusschere, and S. Biesemans, IMEC, Leuven, Belgium

In this work, we present a methodology for characterizing the impact of circuit layout style, technology options, device engineering and temperature on the circuit power-delay trade-off. Experimental results, supported by modeling work, show that the gap between the technology and circuit communities can be closed with the proposed methodology and that process as well as circuit layout improvements can lead to a significant gain in circuit speed at fixed power levels

9:10 Field-Configurable Test Structure Array (FC-

6.3 TSA): Enabling Design for Monitor, Model and Manufacturability, K.Y.Y. Doong, J. Bordelon*, K-J. Chang**, J.J. Hung, C.C. Liao, S.C. Lin, P.S. Ho, S.Hsieh, and K.L. Young, Taiwan Semiconductor Manufacturing Corporation, Shinchu, Taiwan, * Stratosphere Solutions Inc, Sunnyvale USA, **National Tsing University, Shinchu, Taiwan.

This work is designated to provide a common frame work of test chip design for technology development and process routine monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12x25 and 40x25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor test structures are reviewed and corresponding models are discussed.

9:30 A 65nm Random and Systematic Yield Ramp

6.4 Infrastructure Utilizing a Specialized Addressable Array with Integrated Analysis Software, G. Yeric, M. Hall, J. Garcia*, S. Agarwal*, B. Mitchell*, E. Wolf**, M. Karthikeyan***, S. Fox***, HPL Technologies, Austin, TX, *HPL Technologies, Dallas, TX, ** HPL Technologies, Bedford, MA, ***IBM Systems and Technology Group, Hopewell Junction, NY

In order to rapidly ramp 65nm random and systematic yield, an addressable array characterization circuit with dedicated analysis software has been designed and deployed. The use and results of both array and software will be discussed in this paper.

9:50 6.5 Scribe Characterization Vehicle Test Chip

6.5 for Ultra Fast Product Wafer Yield Monitoring

C. Hess, A. Inani, Y. Lin, M. Squicciarini*, R. Lindley**, N. Akiya***, PDF Solutions, Inc. San Jose, CA, *PDF Solutions, Desenzano, Italy, ** PDF Solutions, San Diego, CA, and *** PDF Solutions, Kanagawa, Japan

Sub 100nm technology nodes face more wafer to wafer and lot to lot variability. 300nm wafer manufacturing also faces larger within wafer spatial trends. Monitoring those issues on a per layer basis as well as correlating them to the product yield is key for significant yield improvements. A novel Characterization Vehicle (CV) has been developed, which is being used in the scribe line of product wafers. This Scribe CV test chip achieves an extremely efficient placement of defect sensitive test structure by arranging those in all layers underneath probing pads that are implemented in the top metal layer only. Placed next to product chips all Scribe CV test chips on a wafer can be tested in less than 5 minutes per 300nm wafer. Data analysis unveils layer specific defect densities and fail rates, spatial wafer trends, excursion wafers, and die specific shifts in layer specific parameters like sheet resistance.

BREAK

SESSION 7: CD METROLOGY

10:40 a.m. – 12:00 p.m.

Co-Chairs: Loren Linholm and

A.J. Walton, University of Edinburgh

10:40 Invited Paper:

7.1 What's So Hard about Lithography?

Chris Mack, Founder, FINLE Technologies, former VP of Lithography at KLA-Tencor, adjunct professor at The University of Texas at Austin

11:10 Comparison of Optical and Electrical

7.2 Measurement Techniques for CD Metrology on Alternating Aperture Phase-Shifting Masks, S. Smith, M. McCallum*, A.C. Hourd**, J.T.M. Stevenson, A.J. Walton and A. Tsiamis, The University of Edinburgh, Edinburgh, Scotland, *Nikon Precision Europe, and **Compugraphics International Ltd.

This paper presents the results of a comparison of optical and electrical techniques for CD metrology on alternating aperture phase shifting masks. Initial results show that the phase shifting trenches have a detrimental effect on the optical measurements. In addition the optical metrology system appears to have problems with the measurement of the narrowest isolated features.

11:40 Fabrication of a Novel Copper Test Structure

7.3 for Electrical Critical Dimension Reference, B.J.R. Shulver, A.S. Bunting, L.I. Haworth, A.M. Gundlach, A.W.S. Ross, A.J. Snell, J.T.M. Stevenson, A.J. Walton, R.A. Allen*, and M.W. Cresswell*, University of Edinburgh, Edinburgh, Scotland and National Institute of Standards and Technology, Gaithersburg, MD

A novel copper damascene process is reported for the implementation of ECD reference material. The technique has been illustrated through the use of RIE to create initial silicon structures, with full implementation utilizing anisotropic wet etching of <110> silicon to yield features with vertical sidewalls. Results demonstrate that this method produces copper lines which can measured both electrically and by TEM to extract linewidth values. The process described in this paper can be applied to any damascene compatible material for developing electrical linewidth measurement reference material.

12:00 BUFFET LUNCH in the Exhibit Hall

SESSION 8 – MEMS

1:15 p.m. – 2:55 p.m.

Co-Chairs: Yoshio Mita, University of Tokyo and

Robert Ashton, White Mountain Labs

ICMTS 2006 SPECIAL PRESENTATION – Yoshio Mita

1:35 Characterization of Dielectric Charging in RF

8.1 MEMS, R.W. Herfst, H.G.A. Huizing, P.G. Steeneken, and J. Schmitz*, Philips Research Laboratories, Eindhoven, The Netherlands and *University of Twente, Enschede, The Netherlands

Our research comprises a study on charge injection by stressing the dielectric with electric fields on the order of 1 MV/cm, and using a new method to measure the effects it has on the C-V curve. By determining the voltage shift of the minimum of the C-V curve instead of the pull-in voltage, dielectric charging can be studied with no side effects due to the measurement.

1:55 MEMS Test Structure for Measuring Thermal

8.2 Conductivity of Thin Films, L. La Spina, N. Nenadovic, A. W. van Herwaarden*, H. Schellevis, W. H. A. Wien, and L. K. Nanver, DIMES - Delft University of Technology, Delft, The Netherlands and *Xensor Integration, Delft, The Netherlands

A novel test structure and measurement procedure is presented with which the lateral thermal conductivity of thin films can be easily and accurately extracted. The extraction procedure is discussed in detail and supported by numerical simulations and analytical calculations. Experimental examples are given for the determination of the thermal conductivity of Al, AlN, and p-type polysilicon thin films.

2:15 Test Structures for the Characterisation of

8.3 MEMS and CMOS Integration Technology, H. Lin, A.J. Walton, C.C. Dunare, J.T.M. Stevenson, A.M. Gundlach, University of Edinburgh, Edinburgh, Scotland

Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to provide an integrated system. This requires a low temperature bonding capability along with CMP planarisation and wafer thinning processes which have been demonstrated. The last step in the integration process is to bring electrical connections to the top surface and also demonstrate interconnect between the wafers. Test structures to evaluation this process have been proposed and the measurement results will also be presented.

2:35 A Reliable Bulk Knife-Edged Greek Cross Test

8.4 Structure for as-Deposition Self-Patterning of New LSI Materials, T. Harada, K. Ito, T. Shibata and Y. Mita, University of Tokyo Shibata-Mita Laboratory, Tokyo Japan

A knife-edged Greek-Cross sheet resistance test structure is proposed. By the entrant knife-edge, new material layer is self-patterned as-deposition thus heat-cycle and chemical test becomes possible without degradation by lithography. The test bed is bulk-micromachined for robustness and to pass Joule heat perpendicularly through the embedded silicon heat-sink, that is a critical issue to minimize resistance variation. Together with IV-extrapolation method, resistance curve is linearized thus representative value with <1% of least-squares error is obtainable.

2:55 BREAK

SESSION 9 – MATCHING

3:25 p.m. – 4:45 p.m.

Co-Chairs: Hans P. Tuinhout, Philips Research and

Mark Poulter, National Semiconductor Corp.

3:25 Impact of Emitter Resistance Mismatch on

9.1 Base and Collector Current matching in Bipolar Transistors, S. Danaie, A. Perrotin, G. Ghibaudo*, J-C. Vildeuil, G. Morin, and M. Laurens, STMicroelectronics, Crolles, France and *IMEP/CNRS, Grenoble, France

We characterize bipolar transistor matching at medium and high current levels using an HF test structure. We demonstrate the predominant impact of emitter resistance mismatch on base and collector current matching at high current. To do this, we simulate base and collector mismatch thanks to the experimental values of emitter access resistance and its variations. The results of these simulations are successfully compared to the experimental values.

3:45 High-Frequency Measurements of the

9.2 Mismatch on the Y-parameters of High-Speed SiGe:C HBTs, L.J. Choi, R. Venegas and S. Decoutere, IMEC, Leuven, Belgium

The performance of analog circuits operating at high frequencies is limited by device mismatch at these frequencies. In this paper, high-frequency measurements of the mismatch on the Y-parameters of bipolar transistors are discussed. After investigation of the impact of the deembedding structures and measurement accuracy, the RF matching behavior of a 200 GHz SiGe:C HBT is characterized over a wide range of frequencies and biasing conditions. Mismatch on the cut-off frequency and small-signal parameters are extracted.

4:05 High Frequency Mismatch Characterization

9.3 on 170 GHz HBT NPN Bipolar Device, A. Perrotin, D. Gloria, S. Danaie, F. Pourchon, and M. Laurens, STMicroelectronics, Crolles, France

This paper describes a high frequency parametric mismatch approach on BJT able to reach Ft = 170GHz. All results obtained are complementary and well link with the mismatch extract from DC measurement and in good agreement with the model parameters. In order to extract this result, we have developed new test structure and parameter extraction.

4:25 Improved Methodology for Better Accuracy on

9.4 Transistors Matching Characterization, A. Cathignol*,**, K. Rochereau***, S. Bordez*, and G. Ghibaudo**, *STMicroelectronics, Crolles, France, **IMEP, Grenoble, France, and ***Philips Semicondctors, Crolles, France

In this paper, an improved methodology for the characterization of matching parameter in MOSFET and bipolar tyransistors is presented. Because of their statistical nature, only estimation of matching parameters can be provided from given measurements. Considering general σ_∆p = A_p 1 transistor matching model, the aim of this paper is to discuss for the first time the most relevant matching parameter A_p estimation accuracy. Dispersion on A_p estimation when conventional least squares regression on σ_∆p vs 1/ plots is used is analytically characterized and verified with Monte-Carlo simulations. Then it is shown that replacing the conventional least squares regression by a weighted least squares regression leads to increased accuracy on A_p estimation and consequently allows a better detection of physical effects responsible for mismatch.

6:30 CONFERENCE BANQUET at Salt Lick BBQ

Buses will depart from the main lobby at 5:30 p.m.

and return around 9:30 p.m.

THURSDAY, MARCH 9

PLENARY SESSION

8:30 a.m. – 9:00 a.m.

Test Vehicle Implementation for the 65nm Technology and Beyond, Konrad Young, Director, TSMC R&D

The stronger DFM effects and extra devices require additional test structures, characterization, and resource management for the advanced technology development. This talk will describe the challenges, the design methodology, and the implementation in the 65nm technology development and beyond.

SESSION 10– DEVICE CHARACTERIZATION

9:00 a.m. – 10:40 a.m.

Co-Chairs: Yoshiaki Hagiwara, Sony Corp. and

Charles N. Alcorn, BAE Systems

9:00 Test structure Design for Measuring Electron

10.1 and Hole Mobilities at Very High Injection, G.D. Licciardo, University of Salerno, Salerno, Italy

In this paper is presented a new test structure designed to overcome the limitation of an existing measurement method of the carrier-carrier scattering mobility. The proposed test device allows very accurate control of carrier concentrations without limitations on the test structure geometries. Comparisons of simulations with a well known analytical mobility model show the good accuracy of the proposed test structure in measuring electron and hole mobilities till to very high injection levels. First experimental results of the technique are presented.

9:20 A Test Structure to Separately Analyze

10.2 CMOSFET Reliabilities Around Center and Edge Along the Channel Width, T. Ohzone, E. Ishii, T. Morishita, K. Komoku, T. Matsuda* and H. Iwata*, Okayama Prefectural University, Soja, Japan and *Toyama Prefectural University

A test structure to separately analyze the hot-carrier-induced CMOSFET reliability around the center or the isolation-edge along the channel width was proposed. The test structure contains four MOSFETs; [A] and [D] with a short and a long channel-length all over the channel width, [B] with the short and the long channel-length around the center and the both isolation-edges, respectively, and [C] with the channel-length regions vice versa to [B]. The reliability data were categorized into three; [A], [B]/[C] and [D], which mean that the reliabilities are nearly the same around the center or the edge for the CMOSFETs.

9:40 New 1/F Gate Tunneling Current Noise Model of

10.3 Ultrathin Oxide MOSFETs, F. Martinex, S. Sloliveres, C. Leyris, M. Valenza, CEM2 – Universite Montpellier II, Montpellier, France

An analytical model for 1/f gate noise is developed and applied to the simulation of ultra-thin MOSFETs. The proposed model is based on trapping–detrapping process and uses surface potential modeling including quantum mechanical and gate polydepletion effects. The developed model reproduces experimental behaviors. Moreover, this model is scalable and could be implemented in conventional circuit simulators.

10:00 Dielectric Relaxation Characterization and

10.4 Modeling in Large Frequency and Temperature Domain. Application to 5 fF/µm² Ta2O5 MIM Capacitor, J-P. Manceau, S. Bruyère, E. Picollet, M. Minondo, C. Grundrich, D. Cottin, M. Bely, STMicroelectronics, Crolles, France

This paper deals with 5fF/µm² Ta2O5 MIM (Metal – Insulator – Metal) dielectric relaxation characterization and modeling. A dedicated test chip, focusing on the reduction of all parasitic elements and which can be accurately simulated, allows us to properly measure the associated memory effect and to extract the added RC poles of the model. Through 6 added RC branches, the dielectric relaxation is modeled over 6 time decades and the whole voltage and temperature operation range. The good agreement of this model with MIM capacitance versus frequency measurement validates this approach.

10:20 Impact of Neighbor Components Heating on

10.5 Power Transistor Electrical Behavior, H. Beckrich, S. Ortolland, D. Pache, D. Céli, D. Gloria, T. Zimmer*, STMicroelectronics, Crolles, France and Université Bordeaux, Talence, France

Both reduction in device sizes and enhanced increase in current densities lead to concern about the impact of self-heating effect on device electrical characteristics. Moreover in power transistors applications, devices are connected in parallel, which follows to also consider thermal interaction between devices. In this study a dedicated structure is designed in order to investigate both thermal phenomena and their effect on electrical measurements. Measurements validate a SPICE model taking into account temperature variation induced by self-heating and thermal coupling.

10:40 BREAK

SESSION 11 – CAPACITANCE

11:10 a.m. – 12:30 p.m.

Co-Chairs: Jurrian Schmitz, University of Twente and

Yoshiaki Hagiwara, Sony Corporation

11:10 Analogue Characterization of Horizontal Bars

11.1 Capacitors for Smart Power Applications, Z. Ning, H.-X. Delecourt, L. De Schepper, D. Tack, B. Desoete, and R. Gillon, AMI Semiconductor, Oudenaarde, Belgium

Horizontal bars capacitors are important for smart power technologies. To perform an analogue characterization of the capacitors at different temperatures and bias voltages, a novel technique based on CBCM has been developed. The unit capacitance, the temperature coefficients and the voltage linearity coefficients of the horizontal bars capacitors have been successfully extracted by the technique. The technique is proven with high resolution, high flexibility and low cost.

11:30 Novel Test Structures for On-Chip

11.2 Characterization of Coupling Capacitance Variation by In-and Anti-Phase Crosstalk in Multi-Level Metallization, H-D. Lee, H-H. Ji, I-S. Han, H-S. Joo, D-M. Kim*, S-H. Park**, H-S. Lee**, W-J. Ho**, D-B. Kim**, I-H. Cho**, S-Y. Kim**, S-B. Hwang**, J-G. Lee**, and J-W. Park**, Chungnam National University, Daejeon, Korea, *Korea Institute for Advanced Study, Seoul, Korea and **MagnaChip Semiconductor Inc., Choongbuk, Korea

Novel test structure is proposed for on-chip evaluation of the crosstalk-induced variation of coupling capacitance in multi-fanout and global interconnect lines. Then, it is experimentally shown that the crosstalk-induced variation of coupling capacitance, C_C can be larger than the static coupling capacitance, C_C for both multi-fanout and global interconnect using the novel on-chip test structures. HSPICE simulation is performed to confirm the experimental data.

11:50 A Comprehensive Model to Accurately

11.3 Calculate the Gate Capacitance and The Leakage from DC to 100 Mhz for Ultra Thin Dielectrics, L.Pantisano, J.Ramos, Ph.J.Roussel, W.Sansen*and G.Groeseneken, IMEC, Leuven, Belgium and *University of Leuven, Leuven Belgium

A straightforward model and experimental methodology to extract simultaneously the gate capacitance and the gate leakage is presented for ultra thin oxides. Parasitic effects at high frequencies are minimized using a transmission-like approach while a robust extraction algorithm solves eventual instrument inaccuracies.

12:10 RF-CV Measurements on Metal Gate

11.4 Capacitors, R. Bankras, M. Tiggelman, M. Negara*, G. Sasse, and J. Schmitz, University of Twente, Enschede, The Netherlands, *Tyndall National Institute, Cork, Ireland

Gate leakage has complicated the layout and measurement of C-V test structures. In this paper the impact of metal gate introduction to C-V test structure design is discussed. The metal gate allows for wider-gate structures and for the application of n⁺ -p⁺ diffusion edges. We show both theoretically and with experimental data, that both design modifications lead to a test structure with less overall area, and higher quality factors at the higher measurement frequencies.

12:40 CLOSING REMARKS AND BEST PAPER ANNOUNCEMENT

CONFERENCE COMMITTEE

GENERAL CHAIR

Bill Verzi

Agilent Technologies