The tutorial course of ICMTS 2013 is traditionally held at the first day of the ICMTS. This year, the attendees can learn from the fundermental knowledge to test LSIs and desices on test structures, CAD tools, and interface circuits, as well as emerging technologies such as organic transistor circuits and image sensors.
| 8:45 - 18:00 | Registration |
| 9:30 | Welcome address |
| 9:40 |
1. Introduction to Test Structures
- Anthony J. Walton, University of Edinburgh, Scotland |
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This presentation will begin with a review of test structures detailing their history and hot topics over the past 20 years. The presentation will include the development of test structures for measuring sheet resistance, line width and contact resistance. Measurement and equipment developments will also be addressed focusing on procedures for obtaining accurate and repeatable measurements.
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Prof. Anthony J. Walton
Anthony J. Walton is professor of Microelectronic Manufacturing in the School of Engineering and Electronics at the University of Edinburgh.¡¡ He has been actively involved with the semiconductor industry in a number of areas associated with silicon IC technology and micro-systems. Over the past 30 years he has had a direct interest in the design, fabrication and measurement of microelectronic test structures and has taken an active role in the organization of ICMTS. He played a key role in setting up the Scottish Microelectronics Centre (SMC) which is a purpose built facility for R&D and company incubation consisting of approximately 300 m2 of class 10 cleanrooms. Companies that have successfully incubated in the Centre include MED, Memsstar and Oligon.
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| 11:00 |
2. Very Basics of IO Buffers
- Dr. Toru Nakura, VLSI Design and Design Center, the University of Tokyo, Japan.
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IO buffers are located between LSI cores and PCB boards. A core transistor size shrinks into several-tenth nm range while a package or a board size remains in mm range, and their govering physical laws are different. IO buffers are the interface between the different physical worlds, and the required functions for IO buffers are not only signal transfer between LSI chips, but also ESD protection. This tutorial includes a basic transmission line theorem with termination, ESD issues, kinds of IO buffers and how to assign an IO pin distribution for better signal quality.
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Dr. Toru Nakura
Toru Nakura received the B.S., M.S. and Ph.D. degree in electronic engineering from the University of Tokyo, Tokyo, Japan, in 1995, 1997 and 2005 respectively. He has worked for industry as a circuit designer as well as an EDA tool developer, then he is currently an associate professor at VDEC (VLSI Design and Education Center) in the University of Tokyo. His research interest includes signal integrity and reliabllity of VLSI design. He received Best LSI IP Design Award organized by Japanese semiconductor companies and Nikkei-BP in 2005, Best Paper Award in IPSoC 2005, and IEICE Best Paper Award in 2005.
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| 12:00 | Lunch |
| 13:20 |
3. Introduction to Automated Test Structure Design
- Larg H. Weiland, PDF Solutions Inc.
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Efficient ways have to be found to design and verify test structures when dealing with process development and process monitoring of advanced technology nodes. This tutorial will focus on approaches to automatically generate test structures by comparing different commercial and open source CAD tools and their scripting APIs. A brief example will be presented to automatically design a test structure. Also, verification approaches of test structures will be briefly discussed using standard LVS/DRC tools.
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Dr. Larg H. Weiland
Dr. Weiland received the diploma degree (M. S.) in physics and the Dr.-Ing. (Ph. D.) degree in computer science from the Karlsruhe Institute of Technology (KIT), Germany in 1992 and 1998, respectively. In 1992 he was a founding member of the Defect Diagnosis Group at the Institute of Computer Science and Engineering (formerly: Institute of Computer Science and Fault Tolerance) at the KIT. In 1998 he joined PDF Solutions Inc. in San Jose, CA, USA. As a fellow he is responsible to provide technical direction and guidance for design automation product development. This includes creating design architectures and efficient workflow automation systems for design of experiment (DOE) composition for semiconductor yield enhancement, process optimization and process ramps as well as automated test structure design solutions for state of the art semiconductor technology nodes like 14mn and below (design, place, route, verification, documentation and testing). Dr. Weiland published more than 40 conference and journal papers and holds various patents. He is member of the IEEE and the Electron Devices Society. He has served as conference chair and in the technical committee of several semiconductor manufacturing related conferences. He was the Technical Chair of the 2012 International Conference on Microelectronic Test Structures (ICMTS).
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| 14:40 |
4. Emerging Applications and Design Challenges of Organic Electronics
- Dr. Makoto Takamiya, Institute Industrial Science, the University of Tokyo
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Organic transistors are suitable for large area, flexible, and distributed electronics applications. In this tutorial, emerging applications of the organic electronics such as (1) surface electromyogram measurement sheet for prosthetic hand control, (2) insole pedometer with piezoelectric energy harvester, and (3) 100-V AC energy meter are introduced. The circuit design challenges and the test structures specific to the organic transistors are discussed.
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Dr. Makoto Takamiya
Makoto Takamiya received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 1995, 1997, and 2000, respectively. In 2000, he joined NEC Corporation, Japan, where he was engaged in the circuit design of high speed digital LSI's. In 2005, he joined University of Tokyo, Japan, where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power RF circuits, the ultra low-voltage logic circuits, the low-voltage power management circuits, and the large area and flexible electronics with organic transistors. He is a member of the technical program committee for IEEE Symposium on VLSI Circuits. He received 2009 and 2010 IEEE Paul Rappaport Awards.
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| 16:00 |
5. Design of CMOS image sensor and related surface-sensing sensors with
standard CMOS technology
- Takashi Tokuda, Graduate School of Materials Science, Nara Institute of Science and Technology
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This lecture is started with the design basics of CMOS image sensor
using standard CMOS technology and common design tools. Then, functional
extension of CMOS image sensor-based surface-sensing (on-chip sensing)
sensors are presented and discussed.
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Dr. Takashi Tokuda
Dr. Takashi Tokuda is Associate Professor of Graduate School of Materials Science, Nara Institute of Science and Technology. He got his Bachelor in March 1993 from School of Electrical and Electronic Enginering, Faculty of Engineering, Kyoto University, JAPAN, then got Master degree in March 1995 from Department of Electronic Science and Engineering, Graduate school of Engineering, Kyoto University, then Ph.D in March 1998 from Department of Electronic Science and Engineering, Graduate school of Engineering, Kyoto University.
After his graduation he was a Postdoctoral Fellow, Japan Society for the Promotion of Science in 1998 then appointed as Assistant Professor, Graduate School of Materials Science of Nara Institute of Sicence and Technology in April 1999, then become an Associate Professor at Graduate School of Materials Science,
Nara Institute of Sicence and Technology in April, 2008.
His research interest includes CMOS integrated image sensors and systems.
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| 17:10 | Wrap-Up and Conclusion |
| 18:00- | Continues to welcome Reception |
| 9:10 |
An Integrated CMOS-MEMS Probe having Two-Tips per Cantilever for Individual Contact Sensing and Kelvin Measurement with Two Cantilevers |
| 1.1 |
Kota Hosaka, Satoshi Morishita, Isao Mori, Masanori Kubota, and Yoshio Mita
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The University of Tokyo, Japan |
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The MEMS probe having two tips per cantilever needle is proposed to enable four-terminal (Kelvin) measurement using only two needles. The tips are 5μm in height and placed with 20μm of distance on the 500μm-long, 50μm-wide cantilever. The probe is post-processed on a low cost CMOS circuit, and the system may provide many new features such as individual touch force sensing and probe contact detection.
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| 9:30 | Characterization and Integration of Parylene as an Insulating Structural Layer for High Aspect Ratio Electroplated Copper Coils |
| 1.2 |
R. Walker, E. Sirotkin, I. Schmueser, J.G. Terry, S. Smith, J.T.M. Stevenson and A.J. Walton
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The University of Edinburgh, UK
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This paper reports the development of processing methods and test structures for the characterisation and evaluation of Parylene-C as an insulating structural layer material for integration with planar micro-inductors. The process involves the filling of high aspect ratio gaps between copper structures with Parylene and subsequent chemical mechanical planarisation. A test chip has been designed to characterise this process and the results presented. Subsequently complete micro-inductors, with magnetic cores, have been fabricated to demonstrate the capability of the process.
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| 9:50 |
Micromechanical Test Structures for the Characterization of the Magnetic Response of Electroplated NiFe Cantilevers and their Viability for use in MEMS Switching Devices
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| 1.3 |
G. Schiavone, J. Murray, J.G. Terry, S. Smith, M.P.Y. Desmulliez and A.J. Walton
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The University of Edinburgh, UK
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This work presents the fabrication of a series of test devices aimed at demonstrating the viability of electroplated NiFe freestanding structures for use in magnetically actuated MEMS switches. Preliminary results show promising actuation responses and further testing will enable the quantitative measurement of these characteristics. In addition, this may allow for the mechanical characterization of freestanding structures in other materials by means of magnetic actuation, simply by depositing small quantities of NiFe or other magnetic materials in convenient areas of existing devices.
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| 10:10 |
Investigation of Devices for In-Vivo Energy Harvesting through Blood Flow Excitation
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| 1.4 |
Rosemary O’Keeffe, Nathan Jackson, Alan Mathewson, Kevin McCarthy
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University College Cork, Ireland
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Test structures were designed based on previously designed procedure for highly efficient AlN piezoelectricity generation. These devices were based on FEM models and have been used to determine the feasibility of in-vivo energy harvesting from blood flow as well as used to optimize the models for future generations of devices.
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| 10:30 |
A New Measurement Set-up to Investigate the Charge Trapping Phenomena in RF MEMS Packaged Switches
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| 1.5 |
Marco Barbato, Valentina Giliberto, and Gaudenzio Meneghesso
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University of Padova, Italy
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In this work we develop a new measurement set up able to predict the lifetime of packaged ohmic RF MEMS submitted to long actuation periods. Experimental results were carried out for long time period in order to verify the degradation law relates to charge trapping and stiction problems on cantilever and clamped-clamped switches.
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10:50 - 11:00 Exhibit Presentations
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11:00 - 11:20 Break and Exhibit Inspections
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| 11:20 |
Test Structure and Analysis for Accurate RF-Characterization of Tungsten Through Silicon Via (TSV) Grounding Devices
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| 2.1 |
Volker Blaschke and Hadi Jebory
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TowerJazz, Newport Beach, California, USA
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We present an analysis on the extraction of the through silicon via (TSV) inductance from single port and two port S-parameter results. The test structure design is shown to significantly impact the extracted value and could cause inaccurate results and subsequently errors in the Spice model if not accounted for. We will show that an analytical model of the return circuit loop that the TSV forms with the test structure, does provide a useful assessment of the accuracy of the measured results. This analysis further provides important input for test structure design and when to use single port or two port test structures for TSV measurement.
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| 11:40 |
Test Structures for Electrical Evaluation of High Aspect Ratio TSV Arrays Fabricated Using Planarised Sacrificial Photoresist
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| 2.2 |
R. Zhang, Y. Li, C.C. Dunare, A.S. Bunting, S. Smith, J.T.M. Stevenson, A.J. Walton |
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The University of Edinburgh, UK
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An improved bottom-up electroplating technique has been successfully developed for the fabrication of TSV arrays with about 10:1 aspect ratio. 125,500 TSVs are formed in the area of a 6×6cm square with a pitch of 170 μm. A method of visually inspecting the via yield is presented and Kelvin test structures and contact chain test structures have been fabricated to electrically evaluate single and multiple TSVs respectively.
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| 12:00 |
A Novel Silicon Interposer Capable of Measuring the Designs with Contacts on Both Side of Wafer |
| 2.3 |
Jaber Derakhshandeh, Negin Golshani, Lis K. Nanver, Loek A. Steenweg, Wim van der Vlist
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Delft University of Technology, Netherlands
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In this paper we report the design and fabrication process of a novel silicon based interposer suitable for designs where contacts are in the both sides of wafer. This interposer transfers all contacts to the one side of the wafer so that the measurement can be done using one sided probe stations.
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12:20 - 13:50 Lunch and Exhibit Inspections
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| 13:50 | Characterization of Capacitance Mismatch Using Simple Difference Charge-Based Capacitance Measurement (DCBCM) Test Structure |
| 3.1 |
Ken Sawada1, Geert Van der Plas2, Yuichi Miyamori3, Tetsuya Oishi3, Cherman Vladimir2, Abdelkarim Mercha2, Verkest Diederik2, and Hiroaki Ammo3 |
| 1Sony Corporation to IMEC |
| 2IMEC, Belgium |
| 3Sony Corporation, Japan |
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We proposed new difference charge-based capacitance measurement (DCBCM) test structures for measuring capacitance mismatch. In DCBCM parasitic components can be eliminated and we can measure 100aF mismatch with 7.2aF accuracy. We demonstrate accurate mismatch characteristics on oltage-dependent capacitances. DCBCM gives measurement methods suitable for evaluating capacitance mismatch beyond 20nm node.
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| 14:10 | Comparison of C-V Measurement Methods for RF-MEMS Capacitive Switches |
| 3.2 | Jiahui Wang, Cora Salm, and Jurriaan Schmitz |
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University of Twente, Netherlands
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The applicability of several capacitance-voltage measurement methods is investigated for the on-wafer characterization of RF-MEMS capacitive switches. These devices combine few-picofarad capacitance with a high quality factor. The standard quasistatic and high-frequency measurements are employed, as well as the recently introduced very-low-frequency method. Significant differences are found around the pull-in and pull-out voltages.
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| 14:30 |
Effective Channel Length Estimation Using Charge-Based Capacitance Measurement
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| 3.3 |
Katsuhiro Tsuji and Kazuo Terada |
| Hiroshima City University, Japan |
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An effective channel length is estimated from the C-V curves of actual size MOSFETs which are measured using charge-based capacitance measurement (CBCM). To evaluate the accurate capacitances between the gate and the channel of sample MOSFETs, their parasitic capacitances are removed by using the test MOSFETs having various channel size and special test structures. A good linear relation between the gate-channel capacitance and the design channel length is obtained and then, the effective channel length is estimated from it. It is found that the obtained effective channel length is shorter than that extracted by the conventional channel resistance method.
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| 14:50 |
A New Ultra-Fast Single Pulse Technique (UFSP) for Channel Effective Mobility Evaluation in MOSFETs
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| 3.4 |
Z. Ji, J. Gillbert, J. F. Zhang, and W. Zhang
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Liverpool John Moores University, UK
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A new technique is proposed for mobility evaluation to overcome the shortcomings of conventional techniques. By measuring Id and Cgc simultaneously within 3μs, it removes adverse impact of Vd on mobility, avoids cable-switching, and minimizes charge trapping. Besides, it can work on high ‘leaky’ devices without special RF structure.
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15:10 - 15:40 Break and Exhibit Inspections
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| 15:40 |
Optical High Frequency Test structure and Test Bench definition for on Wafer Silicon Integrated Noise Source characterization up to 110 GHz based on Germanium-on-Silicon Photodiode
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| 4.1 |
S. Oeuvrard1, 2, J.-F. Lampin2, G. Ducournau2, L. Virot1, 3, J.M. Fedeli3, J.M. Hartmann3, F. Danneville2, Y.Morandini4, D. Gloria1
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STMicroelectronics, France
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IEMN, France
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CEA LETI, France
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DOLPHIN INTEGRATION, France
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A new Optical-High-Frequency test structure and dedicated test bench have been developed to characterize a Germanium-on-Silicon photodiode intended to be used as an integrated noise source, a first step to Transistor Noise Figure on-wafer extraction. Continuous wave signals have been measured from these photodiodes, with state-of-the-art RF power higher than -20 dBm at 109 GHz.
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| 16:00 |
Measurements of SRAM Sensitivity against AC Power Noise with Effects of Device Variation
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| 4.2 |
Takuya Sawada1, Kumpei Yoshikawa1, Hidehiro Takata2, Koji Nii2, and Makoto Nagata1,3
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| 1Kobe University, Japan |
| 2Renesas Electronics Corporation, Japan |
| 3CREST, JST, Japan |
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SRAM exhibits sensitivity of false operation against static and sinusoidal supply voltage variation. A measurement system in this paper combines direct RF power injection, on-chip power supply voltage monitoring, and built-in self test of SRAM memory operations. The response of bit error rate against voltage variation is quantitatively demonstrated.
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| 16:20 | On the Length of THRU Standard for TRL De-embedding on Si Substrate above 110 GHz |
| 4.3 |
A. Orii, M. Suizu, S. Amakawa, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, and M. Fujishima |
| Hiroshima University, Japan |
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It is known that the THRU standard (a transmission line) used for thru-reflect-line (TRL) calibration/de-embedding for S parameter measurement has to be long enough for it to work reliably. But ideally, TRL standards should occupy as little precious silicon real estate as possible. This paper attempts to experimentally find out how long a THRU is long enough above 110 GHz. The results indicate that a THRU should be 400μm or longer, excluding pads and pad-to-line transitions.
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| 16:40 | Evaluation of 1/f Noise Variability in the Subthreshold Region of MOSFETs |
| 4.4 |
Hans Tuinhout and Adrie Zegers-van Duijnhoven
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| NXP Semiconductors, Netherlands |
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A test module with multiple MOSFET types and different layout implementations is used for studying several under-explored aspects of 1/f noise modeling. Using a commercial noise characterization system, variability of 1/f noise is evaluated in weak-inversion, revealing important subtleties of low frequency noise.
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| 9:00 | Newly developed Test-Element-Group for Detecting Soft Failures of the Low-Resistance-Element using Doubly Nesting Array |
| 5.1 |
Shingo Sato, Hiroki Shinkawata, Atsushi Tsuda, Tomoaki.Yoshizawa, and Takio Ohno
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| Renesas Electronics Corporation, Japan |
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We report newly developed Test-Element-Group for detecting soft failures of low-resistance-element like interconnect via using doubly nesting array. We detected the soft failure of fine via which resistance had about 10 times larger resistance than normal via using this structure manufactured in 40nm CMOS technology.
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| 9:20 | New Methodology for Drain Current Local Variability Characterization using Y Function Method
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| 5.2 |
L. Rahhal1,2 A. Bajolet1, C. Diouf1,2, A. Cros1, J. Rosa1, N. Planes1 G. Ghibaudo2
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| 1STMicroelectronics, France |
| 2IMEP-LAHC, France |
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Y function is well known to overcome the influence of source/drain series resistance (Rsd) in MOSFETs. In this work we present a new methodology for drain current local variability characterization using Y function method. Thus, we demonstrate that the use of Y function statistical variability permits the extraction of Vt and β variability without the influence of Rsd values and the deduction of Rsd variability contribution to the to global drain current variability in strong inversion regime.
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| 9:40 |
A Novel BJT Structure for High-Performance Analog Circuit Applications
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| 5.3 |
Seon-Man Hwang, Hyuk-Min Kwon, Jae-Hyung Jang, Ho-Young Kwak, Sung-Kyu Kwon, Seung-Yong Sung, Jong-Kwan Shin, Jae-Nam Yu and Hi-Deok Lee |
| Chungnam National University, Korea |
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A novel structure is proposed to improve the matching characteristics of bipolar junction transistor (BJT) based on CMOS technology for high performance analog circuit applications. This paper includes the analysis of electrical and matching characteristics in collector current density (JC), base current density (JB) and current gain (β). Although the collector current density JC of the proposed structure is similar to that of the conventional structure, the base current density JB is lower than that of conventional structure, which results in higher current gain. The matching characteristics of the collector current density and the current gain of the proposed structure showed improvement of about 12.22% and 36.43%, respectively compared with the conventional structure.
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| 10:00 |
Reconsideration of the Threshold Voltage Variability Estimated with Pair Transistor Cell Array
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| 5.4 |
Kazuo Terada, Naoya Higuchi and Katsuhiro Tsuji
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| Hiroshima City University, Japan |
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The standard deviation of threshold voltage, ¦ÒVTH, which is estimated with Pair Transistor cell Array (PTA), is examined using the test chip fabricated by 65-nm technology. It is found that the errors are caused by two problems: (1) the problem in the approximation and (2) leak current in the isolation region. Taking them into account, the application of PTA to the test structure in scribe line is studied.
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10:20 - 10:50 Break and Exhibit Inspections
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| 10:50 | Comparison of Electrical Techniques for Temperature Evaluation in Power MOS Transistors |
| 6.1 |
A. Ferrara1, P.G. Steeneken2, K. Reimann2, A. Heringa3, L. Yan3, B.K. Boksteen1, M. Swanenberg2, G.E.J. Koops3, A.J. Scholten2, R. Surdeanu3, J. Schmitz1, R.J.E. Hueting1 |
| 1University of Twente, Netherlands |
| 2NXP Semiconductors, Netherlands |
| 3NXP Semiconductors, Belgium |
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Three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for temperature evaluation in power MOS transistors are experimentally compared. On wafer measurements are performed on an SOI-LDMOS transistor design with embedded sense-diodes in the center and at the edge of the device. As a result, guidelines for the choice of the most adequate technique are provided.
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| 11:10 |
Measurement and Investigation of Thermal Properties of the On-Chip Metallization for Integrated Power Technologies |
| 6.2 |
Martin Pfost1, Cristian Boianceanu2, Dan-Ionu«á Simon2, and Sebastian Sosin2
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| 1Reutlingen University, Germany |
| 2Infineon Technologies, Romania |
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Test structures to determine the influence of the metallization in integrated power technologies with pronounced self-heating are presented and variants with different metal layers and via configurations investigated. The measurement results are supported by numerical simulations, giving valuable insights into the heat flow and cooling capability of the on-chip metallization.
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| 11:30 |
Investigation on Safe Operating Area and ESD Robustness in a 60-V BCD Process with Different Deep P-Well Test Structures |
| 6.3 |
Chia-Tsen Dai and Ming-Dou Ker
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| National Chiao-Tung University, Taiwan |
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Safe operating area (SOA) is one of the noticeable reliability concerns for power MOSFETs during the normal circuit operating conditions. Besides, electrostatic discharge (ESD) reliability is another important reliability issue for the power IC products. To save the layout area of power IC with high-voltage (HV) devices, it is preferable for HV MOSFET to be self-protected without any additional ESD protection device, and to behave wide SOA region. In this work, the impact of deep P-Well (DPW) structure to the electrical SOA (eSOA) and ESD robustness of HV MOSFET has been investigated in a 0.25-μm 60-V BCD process. DPW structure is used to implement the RESURF (reduced surface field) in MOSFET to make it be able to sustain the high operating voltage. From the experimental results in silicon chip, the ESD robustness and wide eSOA of HV MOSFET can be improved by the modified DPW structure.
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| 11:50 | A Test Structure for Analysis of Temperature Distribution in CMOS LSI with Sensing Device Array |
| 6.4 |
T. Matsuda1, H. Hanai1, H. Iwata1, D. Kondo1, T. Hatakeyama1, M. Ishizuka1, and T. Ohzone2 |
| 1Toyama Prefectural University, Japan |
| 2Dawn Enterprise, Japan |
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A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip were measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor were analyzed as well as transient phenomena. The test structure can provide an effective methodology for analysis of fundamental thermal properties in LSIs packaged in various ways.
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12:10 - 13:40 Lunch and Exhibit Inspections
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13:40 - 13:50 ICMTS 2014 Presentation
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| 13:50 | Analysis of Narrow Gate to Gate Space Dependence of MOS Gate-Source/Drain Capacitance by Using Contact-less and Drawn-out Source/Drain Test Structure |
| 7.1 |
Yasuhisa Naruta and Shigetaka Kumashiro |
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Renesas Electronics Corporation, Japan
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A new test structure which can provide voltage to the very narrow source/drain region between adjacent gates by drawing out the source/drain silicide layer has been developed. By using the test structure, the dependence of the gate-drain capacitance (Cgd) on the gate-gate space (Lsp) has been successfully measured until the minimum gate pitch where no contact can be placed. Decrease of Cgd with respect to the decrease of Lsp has been observed and its main cause is identified as the decrease of the gate-drain overlap length.
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| 14:10 | Three- and Four-Point Hamer-type MOSFET Parameter Extraction Methods Revisited |
| 7.2 |
Kjell O. Jeppson |
| Chalmers University of Technology, Sweden |
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In this presentation three-point Hamer type and four-point Karlsson & Jeppson type MOSFET parameter extraction is revisited concerning selection of data points and method robustness. The method for fitting models described by rational functions to measured data proposed by Hamming is also discussed and it is shown how this method calculates its weighted data points. An alternative method where MOSFET resistance values are used instead of current values for the extraction procedure is also investigated in an attempt to increase extraction method robustness. Finally, it is shown how the three point extraction method can be applied not only to the triode region but also to the MOSFET saturation region for separating parameters for the body effect and the velocity saturation.
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| 14:30 | Die-to-Die and Within-Die Variation Extraction for Circuit Simulation with Surface-Potential Compact Model |
| 7.3 |
Y. Ohnari, A.A. Khan, A. Dutta, M. Miura-Mattausch, and H. J. Mattausch |
| Hiroshima University, Japan |
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A 65nm CMOS TEG for die-to-die and within-die variation analysis is reported. From measured Vth and Ion variation data of transistor pairs, die-to-die and within-die microscopic-parameter variations of a surface-potential model are extracted. Consideration of only five microscopic parameters is found sufficient to capture the channel-length dependence of these variations.
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| 14:50 | BSIM4 Parameter Extraction for Tri-gate Si Nanowire Transistors |
| 7.4 |
Chika Tanaka, Masumi Saitoh, Kensuke Ota, and Toshinori Numata |
| Toshiba Corporation, Japan |
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We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes using measurement data. Dependence of source/drain parasitic resistances on transistor geometry and fabrication process can be observed on the extracted parameters. Single sets of parameters can reproduce I-V characteristics with Lg down to 35nm.
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15:10 - 15:40 Break and Exhibit Inspections
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| 15:40 | Benchmarking of a Surface Potential Based Organic Thin-Film Transistor Model against C10-DNTT High Performance Test Devices |
| 8.1 |
T. K. Maiti, T. Hayashi, H. Mori, M. J. Kang, M. Miyake, T. Iizuka, K. Takimiya, M. Miura-Mattausch, and H. J. Mattausch |
| Hiroshima University, Japan |
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In this paper, a surface potential based compact model for organic thin-film transistors (OTFTs) including both tail and deep trap states across the band gap is presented and benchmarked against measured data from high-performance 2,9-didecyl-dinaphtho [2,3-b:2',3'-f] thieno [3,2-b] thiophene (C10-DNTT) based test devices. This model can accurately describe the OTFT test-structure current from week to strong inversion regime.
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| 16:00 | Electrical and Mechanical Characterization of a Large-area All-printed Organic Transistor Active Matrix with Floating-gate-based Non-uniformity Compensator |
| 8.2 |
Tsuyoshi Sekitani, Tomoyuki Yokota, Takeyoshi Tokuhara, Naoya Take, and Takao Someya |
| University of Tokyo, Japan |
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We report electrical and mechanical characterizations of a large-scale, all-printed, ultraflexible organic transistor active matrix on 10-μm thin-film plastic substrates. The printed active matrix comprising printed floating-gate organic transistors have been manufactured utilizing high-definition screen-printing and inkjet-printing. By applying feedback control to the threshold voltages of the floating-gate organic transistors, the circuit can compensate the device-to-device non-uniformity, which is less than 5%. The 230×230mm2printed active matrix circuit comprises 200×200 screen-printed organic transistor cells, and the periodicity is 1.0mm. Because the circuit’s substrate is made of 10-μm thin-film, critical bending radii of less than 0.5 mm are achieved.
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| 16:20 | Greek Cross Test Structures for Ink Jet Printed Electronics |
| 8.3 |
Elkin Díaz, Eloi Ramon, and Jordi Carrabina |
| Universitat Autònoma de Barcelona, Spain |
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This paper reports on usage of Greek cross test structure to characterize inkjet printed electronics circuits. Geometric characteristics extracted from optical characterization can be correlated with electric measurements for square resistance. Design of inkjet printed Greek cross test structure should compensate or reduce the ink coalescence and coffee ring effects. |
| 16:40 | Process Control Monitors for Individual Carbon Nanotube Transistor Fabrication Processes |
| 8.3 |
Kiran Chikkadi, Miroslav Haluska, Christofer Hierold, and Cosmin Roman |
| ETH Zurich, Switzerland |
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The manufacturing yield of carbon nanotube transistors is very sensitive to changes in process parameters, while controlling length, density and orientation of nanotubes simultaneously is still proving elusive in batch fabrication processes. Here, we show an electrode design with a yield of up to 45% working transistors despite our batch fabrication process being based on randomly grown nanotubes. Transistor parameter distributions of 765 devices are shown, demonstrating the potential of our design for process monitoring and control.
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| 9:00 | Automatic Test Methodology to Optimize Operating Conditions and Reliability of Conductive Bridge RAM |
| 9.1 |
A. Toffoli, E. Vianello, G. Molas, L. Perniola, B. De Salvo, and G. Reimbold |
| CEA- LETI, France |
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To evaluate CBRAM technologies, we have implemented test structures including 1T1R cells both single and in array NOR configuration. Appropriated test sequences are combined, to investigate forming, seasoning and endurance phases. Voltages and pulse widths scans are used to investigate and adjust programming parameters, and then smart controlled LRS and HRS cycling explore endurance performances. 1T1R Cells and Matrix test structures offer both quick and high statistical results to evaluate technologies robustness for various applications.
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| 9:20 | Proper Approach to Characterize Retention-after- Cycling in 3D-Flash Devices |
| 9.2 |
Fengying Qiao1, Antonio Arreghini2, Pieter Blomme2, Geert Van den bosch2, Liyang Pan1, Jun Xu1 and Jan Van Houdt2 |
| 1Tsinghua University, China |
| 2IMEC, Belgium |
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We propose a procedure to evaluate retention-after- cycling in 3D-flash devices. The observed ID-VG degradation is compensated by a relaxation phase, consisting in baking samples for 24 hours at 200 °C. The relaxation anneals interface traps and promotes lateral redistribution of charges, allowing proper extraction of device VT and hence more relevant comparison of retention before and after cycling.
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| 9:40 | A Novel Test Structure to Implement a Programmable Logic Array Using Split-Gate Flash Memory Cells |
| 9.3 |
Henry Om’mani, Mandana Tadayoni, Nitya Thota, Ian Yue, and Nhan Do |
| Silicon Storage Technology, USA |
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We developed a novel configurable logic array test structure using a highly scalable 3rd generation split-gate flash memory cell that features low power and fast configuration time. This split-gate SuperFlash® configuration element (SCE) has been demonstrated with a 90nm embedded flash technology. The resulted SCE eliminates need for esoteric fabrication process, sense, and SRAM circuits and reduces configuration time for programmable array (PA) like FPGAs and CPLDs. Additionally, SCE ports inherent the advantages of SST’ s split-gate flash memory technology with compact area, low voltage read operation, low power poly-to-poly erase and source-side channel hot electron (SSCHE) injection programming mechanisms, and superior reliability.
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| 10:00 | On-wafer Integrated System for Fast Characterization and Parametric Test of New-Generation Non Volatile Memories |
| 9.4 |
Erika Covi1, Alessandro Cabrini1, Loris Vendrame2, Luca Bortesi2, Roberto Gastaldi2, and Guido Torelli1 |
| 1Università di Pavia, Italy |
| 2Micron Semiconductor Italia, Italy |
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In new and future generations of Non Volatile Memories such as Phase Change Memories and Resistive-RAMs, having accurate and controllable program pulses is fundamental to adequately characterize the memory cell, since the obtained cell status is a function of the applied pulse parameters. In order to massively test new cells and enhance the conventional instrumentation flexibility, an accurate on-chip pulse generator, able to provide pulses with different amplitude, falling time, and duration, has been designed and experimentally evaluated.
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10:20 - 10:40 Break
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| 10:40 | Tr Variance Evaluation induced by Probing Pressure and its Stress Extraction Methodology in 28nm High-K and Metal Gate process |
| 10.1 |
T. Okagaki, T. Hasegawa, H. Takashino, M. Fujii, A. Tsuda, K. Shibutani, Y. Deguchi, M. Yokota, and K. Onozawa |
| Renesas Electronics Corporation, Japan |
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We discuss characteristics variance in detail, caused by probing stress in 28nm High-K and Metal Gate process. The Vth variation of nch large size transistor increases by 20% comparing with weak probing pressure(~0). Regarding small size transistors, probing stress impact both on Vth fluctuation and on Tpd fluctuation is small. Moreover, we extracted the space distribution of probing stress quantitatively. It is useful to calibrate a stress simulation methodology and to facilitate evaluation of the mechanical strength of the material.
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| 11:00 | Efficient Technique for Si Validation of Level Shifters |
| 10.2 |
Puneet Sharma, Brad Smith, Donald Hall, Mike Nelson and Umesh Lohani |
| Freescale Semiconductor India, India |
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This paper presents a new structure of addressable parametric array to validate level shifter cells. Presented structure is very area efficient and allows direct measurement of input & output voltages. Experimental data confirmed the utility of this approach, validating level shifters in three different power domains including source biasing on the same 22 pad design. The simulation result shows good correlation with the measured data. Being a parametric structure enabled direct measurement of the output voltages, a critical parameter for level shifters.
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| 11:20 | Mosaic SRAM Cell TEGs with Intentionally-added Device Variability for Confirming the Ratio-less SRAM Operation |
| 10.3 |
Hitoshi Okamura, Takahiko Saito, Hiroaki Goto, Masahiro Yamamoto and Kazuyuki Nakamura |
| Kyushu Institute of Technology, Japan |
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MOSAIC SRAM Cell TEGs consisting of memory cells having all combinations of gate sizes of transistors differing by two orders of magnitude were developed with 0.18um CMOS process to verify the operation margins for SRAM circuits. The measured results show the operation of the ratio-less SRAM is completely independent of the size of transistors in the memory cell.
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| 11:40 | Characterization and Simulation of NMOS Pass Transistor Reliability for FPGA Routing Circuits |
| 10.4 |
Christopher S. Chen and Jeffrey T. Watt |
| Altera Corporation, USA |
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In this work, the impact of bias temperature instability is evaluated for routing pass gate circuits. Measured data is compared to aging models to demonstrate the importance of modeling circuit level aging effects. Aging models which are shown to be accurate at the transistor level are inadequate at the circuit level unless frequency dependent aging effects are taken into account.
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12:00 Best Paper Announcement
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Closing Remarks
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12:05 End of Conference
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