|
Paper |
Title |
Authors |
| Session 1 |
Reiability and Array Structures |
|
1-1 |
14nm BEOL TDDB Reliability Testing and Defect Analysis |
T. Kane (IBM) |
|
1-2 |
A Novel Structure of MOSFET Array to Measure Ioff-Ion with High Accuracy and Density |
T. Suzuki et al. (Sony) |
|
1-3 |
Circuit Architecture and Measurement Technique to Reduce the Leakage Current Stemming from Peripheral Circuits with an Array Structure in Examining the Resistive Element |
S. Sato et al. (Kansai U.) |
|
1-4 |
Circuit Architecture and Measurement Technique to Reduce the Leakage Current Stemming from Peripheral Circuits with an Array Structure in Examining the Resistive Element |
M. Ritter and M. Pfost (Reutlingen U.) |
| Session 2 |
Modeling |
|
2-1 |
SPICE Modeling of 55nm Embedded Superflash® Memory Cells |
S. Martinie et al. (CEA-LETI) |
|
2-2 |
Compact Modeling and Parameter Extraction Strategy of Normally-on MOSFET |
T. Umeda et al. (Hiroshima U.) |
|
2-3 |
Modeling ofT-Model Equivalent Circuit for Spiral Inductors in 90 nm CMOS Technology |
J.-W. Jeong et al. (Chungnam National U.) |
|
2-3 |
A Four-Terminal JFET Compact Model for High-Voltage Power Applications |
W. Wu et al. (TI) |
| Session 3 |
Process Evaluation |
|
3-1 |
Accelerating 14nm Device Learning and Yield Ramp Using Parallel Test Structures as Part of a New Inline Parametric Test Strategy |
G. Moore et al. (IBM) |
|
3-2 |
Employing an On-Die Test Chip for Maximizing Parametric Yields of 28 nm Parts |
J. Mueller et al. (Freescale) |
|
3-3 |
Robust Process Capability Index Tracking for Process Qualification |
C. Gu and C. McAndrew (Freescale) |
|
3-4 |
New Compact Model for Performance and Process Variability Assessment in 1 4nm FDSOI CMOS Technology |
Y. Denis et al. (STMicroelectronics) |
|
3-5 |
Silicon Thickness Monitoring Strategy for FD-SOI 28 nm Technology |
A. Cros et al. (STMicroelectronics) |
| Session 4 |
Discussion |
|
4-1 |
A Test Structure for Characterizing the Cleanliness of Glass Beads Using Low-Frequency Dielectric Spectroscopy |
M. Buehler (Decagon Devices) |
|
4-2 |
Development of a Compacted Doubly Nesting Array in Narrow Scribe Line Aimed at Detecting Soft Failures of Interconnect Via |
H. Shinkawata et al. (Renesas) |
|
4-3 |
The Impact of Deep Trench and Well Proximity on MOSFET Performance |
H. Sheng et al. (Freescale) |
|
4.4 |
Withdrawn |
|
|
4-5 |
A Test Structure for Reliability Analysis of CMOS Devices and DC and High Frequency AC Stress |
T. Matsuda et al. (Toyama Prefectural U.) |
|
4-6 |
Measurement and Modeling of IC Self-Heating Including Cooling System Properties |
T. Nishimura et al. (Hiroshima U.) |
|
4-7 |
Elastic Instabilities Induced Large Surface Strain Sensing Structures (EILS) |
Y. Li et al. (Northumbria U.) |
|
4-8 |
Cross-Correlation of Electrical Measurements via Physics-Based Device Simulations: Linking Electrical and Structural Characteristics |
A. Padovani et al. (U. Modena) |
|
4-9 |
NPN CML Ring Oscillators for Model Verification and Process Monotoring |
C. Compton (Macom) |
| Session 5 |
Parameter Extraction |
|
5-1 |
Compact Modeling Solution of Layout Dependent Effect for FinFET Technology |
D. Chen at al. (UMC) |
|
5-2 |
A Simple Method for Characterization of MOSFET Serial Resistance Asymmetry |
D. Tomaszewski et al. (ITE Warsaw) |
|
5-3 |
Threshold Voltage Extraction Method in 2D Devices having a mobility with Power-Law Dependence of Carrier Density |
V. Mosser et al. (ITRON SAS) |
|
5-4 |
Measurement of Vth due to STI Stress and Inverse Narrow Channel Effect at Ultra-Low Voltage in a Variability-Suppressed Process |
Y. Ogasahara et al. (NAIST Japan) |
| Session 6 |
Capacitance |
|
6-1 |
Monitoring Test Structure for Plasma Process Induced Charging Damage Using Charge-Based Capacitance Measurement (PID-CBCM) |
S. Mori et al. (Sony) |
|
6-2 |
A Novel Gate Charge Measurement Method |
A. Mikata, et al. (Keysight) |
|
6-3 |
Capacitance Analysis in 16 nm Process Node |
T. Okagaki et al. (Renesas) |
|
6-4 |
In-line Monitoring Test Structure for Charge-Based Capacitance Measurement (CBCM) with a Start-Stop Self-Pulsing Circuit |
K. Sawada et al. (Sony) |
| Session 7 |
Resistance |
|
7-1 |
Design and Evaluation of a SiCr Thin Film Resistor Matching Test Structure |
H. Tuinhout et al. (NXP) |
|
7-2 |
Characterization of Recessed Ohmic Contacts to AlGaN/GaN |
M. Hajlasz et al. (U. Twente) |
|
7-3 |
Adapted from Four-Point Probe Technique |
J. Lehmann et al. (CEA-LETI) |
|
7-4 |
Sheet Resistance Measurement for Process Monitoring of 400° C PureB Deposition on Si |
L. Qi abd L. Nanver (TU Delft) |
|
7-5 |
Combined Transmission Line Measurement Structures to Study Thin Film Resistive Sensor Fabrication |
A. Tabasnikov et al. (U. Edinburgh) |
| Session 8 |
Emerging Technologies |
|
8-1 |
Test Structures for the Wafer Mapping and Correlation of Electrical, Mechanical, High Frequency Magnetic, and Composition of Electroplated Ferromagnetic Alloys |
E. Sirotkin et al. (U. Edinburgh) |
|
8-2 |
A Fully-Automated Methodology and System for Printed Electronics Foil Characterization |
F. Vila et al. (IMB-CNM) |
|
8-3 |
A Capacitive Based Piezoelectric AIN Film Quality Test Structure |
N. Jackson et al. (Tyndall National Institute) |
| Session 9 |
Circuits |
|
9-1 |
Silicon Measurements of Characteristics for Pass-gate/Pull-down/Pull-up MOSs and Search MOS in a 28 nm TCAM Bitcell |
K. Nii et al. (Renesas) |
|
9-2 |
Test circuit for Accurate Measurement of Setup/Hold and Access Time of Memories |
N. Agarwal (ARM) |
|
9-3 |
Reduction of Overhead in Adaptive Body Bias Technology due to Triple-well Structure based on Measurement and Simulation |
Y. Ogasahara et al. (NAIST Japan) |
|
9-4 |
Sensitivity-Independent Extraction of Vth Variation Utilizing Log-normal Delay Distribution |
A. Islam and H. Onodera (Kyoto U.) |
| Session 10 |
RF |
|
10-1 |
Characterization of Wideband Decoupling Power Line with Extremely Low Characteristic Impedance for Millimeter-Wave CMOS Circuits |
R. Goda et al. (Hiroshima U.) |
|
10-2 |
Observations on Substrate Characterisation through Coplanar Transmission Line Impedance Measurements |
L. Floyd et al. (Tyndall National Institute) |
|
10-3 |
Systematic Calibration Procedure of Process Parameters for Electromagnetic Field Analysis of Millimeter-Wave CMOS Devices |
K. Takano et al. (Hiroshima U.) |
|
10-4 |
Electromagnetic Field Test Structure Chip for Back End of the Line Metrology |
L. You et al. (NIST) |